As is known, level-shifter circuits have an extensive application in electronics, for example, in the cases where it may be desirable to interface two integrated circuits operating at different voltage levels. In storage devices, for example of a flash type with 90-nm CMOS technology, an internal supply voltage is present (the so-called “logic supply voltage Vdd”, with values, for example, between 1 V and 1.35 V). Moreover, to allow modifying (for programming or erasure) and reading the contents of memory cells, higher operating voltages may be used, with values, for example, between 1.6 V and 10 V. Given the different range of voltage values in these storage devices, it may be desirable to use level-shifter circuits, which enable the two, low-voltage and high-voltage, circuits to be interfaced and set in communication in such a way as to reduce damage and breakdown.
Level-shifter circuits of a known type are generally made with high-voltage transistors (i.e., ones able to operate with high voltage values without any breakdown of the corresponding junction oxides). In some cases, level-shifter circuits may be made with a mix of high-voltage transistors and low-voltage transistors (i.e., ones able to operate without risking breakdown for voltage values not higher than a given threshold voltage, typically corresponding to the logic supply voltage Vdd). In general, these circuits have an important limitation in that they typically do not enable high-frequency switchings, as may, instead, be desired, for example, in phase-generator circuits of a charge pump (which operate, for example, at clock frequencies of from 50 MHz up to even 150 MHz).
As is known, charge-pump circuits are widely used to obtain output voltage values higher than a given input voltage (operating basically as DC-DC boost converters), exploiting the use of capacitors as charge-accumulation elements, to which suitable timing signals, or phase signals are supplied (switching periodically between a low voltage value and a high voltage value). For example, charge-pump circuits are used in flash-memory devices for generating the high voltage values for carrying out the operations of reading, writing, and erasure of data, starting from the low values of the internal supply voltage.
FIG. 1 illustrates a level-shifter circuit 1 of a known type, which uses only high-voltage transistors and is designed to shift a low input voltage operating in the range [0; Vdd] into a high output voltage operating in the range [0; VddH], where VddH is a high, or level-shifted, voltage, higher than the logic supply voltage Vdd. In detail, the level-shifter circuit 1 includes a first transfer transistor Mn1, of a high-voltage NMOS type (i.e., with thick gate oxide in such a way as to reduce any breakdown at high voltage values), which is connected between a first reference terminal (set at ground potential, Gnd) and an output terminal OutB, and the gate terminal of which is connected to a first input terminal InA receiving a first phase signal FX. The level-shifter 1 includes a second transfer transistor Mn2, of a high-voltage NMOS type, which is connected between the first reference terminal set at ground potential and a further output terminal OutA, and the gate terminal of which is connected to a second input terminal InB receiving a second phase signal FN. A third transfer transistor Mp1, of a high-voltage PMOS type, is connected between a second reference terminal (set at the high voltage VddH) and the output terminal OutB, and the gate terminal of which is connected to the output terminal OutA. The level-shifter 1 further includes a fourth transfer transistor Mp2, of a high-voltage PMOS type, which is connected between the second reference terminal (set at the high voltage VddH) and the output terminal OutA, and the gate terminal of which is connected to the output terminal OutB (it should hence be noted that the third and fourth transfer transistors Mp1, Mp2 are connected in latch configuration). It should moreover be noted that, for the purposes of operation of the level-shifter circuit 1, the distinction between the conduction terminals (drain and source terminals) of the various MOS transistors is typically not important.
The first and second phase signals FX, FN are generated starting from the logic supply voltage Vdd and have complementary values (or values negated with respect to one another). In other words, when the first phase signal FX is at a high value equal to Vdd, the second phase signal FN is at a low value equal to Gnd, and vice versa, when the first phase signal FX is equal to Gnd, the second phase signal FN is, instead, at the high value equal to Vdd. In use, when the first phase signal FX is high (and the second phase signal FN is low), the first transfer transistor Mn1 is on, whereas the second transfer transistor Mn2 is off. Consequently, the output terminal OutB goes to ground Gnd (through switching-on of the first transfer transistor Mn1), whereas the second output terminal OutA goes to VddH (through switching-on of the fourth transfer transistor Mp2), thus switching off the third transfer transistor Mp1.
The behavior of the circuit is similar when the first phase signal FX is low (Gnd) and the second phase signal FN is high (Vdd). The desired level-shifting effect is thus obtained, with the phase signals FX, FN, received at the inputs InA, InB, that switch in the range that goes from Gnd up to Vdd, and the output signals, supplied on the outputs OutA and OutB, that switch in the range shifted upwards that goes from Gnd up to VddH.
U.S. Pat. No. 7,071,730 discloses a variant embodiment of the level-shifter circuit of FIG. 1, designed to render the switchings thereof faster, using a mixed approach, with both high-voltage transistors and low-voltage transistors.
These mixed-approach circuits are, however, unable to switch at high frequency (for example, at a frequency sufficient for generation of the phases in a charge-pump circuit). Moreover, these circuits entail a considerable current consumption linked to crossover currents.